CS401- Computer Architecture and Assembly Language Programming McQs collection Part8
Question No: 1 ( M a r k s: 1 )
Sun SPARC Processor has a fixed ______________ instruction size.
1. 16bit
2. 32bit
3. 64bit
4. 20bit
Question No: 2 ( M a r k s: 1 )
When the subprogram finishes, the ____________________ retrieves the return address from the stack and transfers control to that location.
1. RET instruction
2. CALL instruction
3. POP instruction
4. Jump instruction
Question No: 3 ( M a r k s: 1 )
A 32 bit address register can access upto __________ of memory.
- 1 GB
- 6 GB
- 4 GB
- 2 GB
Question No: 4 ( M a r k s: 1 )
The value of a segment register when the processor is running under protected mode is called
1. segment descriptor
2. segment selector
3. global descriptor table
4. protected register
Question No: 5 ( M a r k s: 1 )
FS and GS are two ___________________ in protected mode.
1. segment registers
2. segment selectors
3. stack pointers
4. register pointers
Question No: 6 ( M a r k s: 1 )
IRQ 0 interrupt have _______________ priority
1. low
2. medium
3. highest
4. lowest
Question No: 7 ( M a r k s: 1 )
IDT stands for ______________________.
1. interrupt descriptor table
2. individual descriptor table
3. inline data table
4. interrupt descriptor table
Question No: 8 ( M a r k s: 1 )
Every bit of line status in serial port conveys _____________ information.
1. different
2. same
3. partial
4. full
Question No: 9 ( M a r k s: 1 )
There are total _______________ bytes in a standard floppy disk.
1. 1444k
2. 1440k
3. 1280k
4. 2480k
Question No: 10 ( M a r k s: 1 )
An 8x16 font is stored in _________________ bytes.
- 8
- 16
- 4
- 20
=============================================================
. Serial Port is also accessible via I/O ports , COM 1 is accessible via ports 3F8-3FF while COM 2 is accessible via 2F8 -2FF.
The first register at 3F8 is the Transmitter holding register if written to and the receiver buffer register if read from.
Other register of our interest include 3F9 whose Bit 0 must be set to enable received data available interrupt and Bit 1 must be set to enable transmitter holding register empty interrupt.
(Transmitter, COM 1, I/O ports , COM2. bit 0 , Buffer , 3FA)
====================================================
No comments:
Post a Comment